Field of the Invention
The present invention relates to digital memory devices, and more particularly to apparatus and methods for programming ECC-enabled NAND flash memory.
Description of Related Art
NAND flash memory has become increasingly popular due to its significant cost advantage. Moreover, NAND flash memory is now available in a variety of different interfaces, ranging from traditional NAND interfaces to low pin count Serial Peripheral Interfaces (“SPI”). However, NAND flash memory is susceptible to bad block conditions and occasional read errors, so that bad block management and error correction code processing is commonly used with such memory.
One implementation of ECC and bad block management during a program operation is disclosed in a publication by Winbond Electronics Corporation, W25N01 GV: SpiFlash 3V 1 G-Bit Serial SLC NAND Flash Memory with Dual/Quad SPI & Continuous Read: Preliminary Revision B, Hsinchu, Taiwan, R.O.C., Nov. 26, 2013. The Program operation allows from one byte to 2,112 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A program operation, which is preceded by a Write Enable instruction, involves two steps: (1) load the program data into the Data Buffer; and (2) transfer the data from the Data Buffer to a specified memory page.
An example of an instruction which loads the program data into the Data Buffer is the “Load Program Data” instruction, which is initiated by driving the /CS pin low, and then shifting in the instruction code “02h” followed by a 16-bit column address and 8-bit dummy clocks, and at least one byte of data.
An example of an instruction which transfers the data from the Data Buffer to the specified memory page is the “Program Execute” instruction, which is initiated by driving the /CS pin low, and then shifting in the instruction code “10h” followed by 8-bit dummy clocks and the 16-bit Page Address. After /CS is driven high to complete the instruction cycle, the self-timed Program Execute instruction commences for a time duration of tPP, which is the time needed for such time-intensive tasks as page program, One-Time Program (“OTP”) Lock, and Bad Block Management (“BBM”). The time tPP is typically about 250 μs, but may be as long as 700 μs. While the Program Execute cycle is in progress, the Read Status Register instruction may be used for checking the status of the Busy bit, which is a logical 1 during the Program Execute cycle and becomes a logical 0 when the cycle completes and the device is ready to accept instructions. When the Program Execute cycle completes, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.
If internal ECC is enabled, all bytes of data on the page and in the extra 64 byte section (spare area) are accepted, but the bytes designated for the error correction code in the extra 64 byte section are overwritten by the ECC calculation.
If another page is to be programmed, another program operation may be carried out by issuing another Write Enable instruction, followed by another “Load Program Data” instruction, followed by another “Program Execute” instruction.